SystemC wrapper above System Verilog TB

[svontop]

Hi all

i have tb in SV and i want to create a wrapper of Systemc above that.

can any one help me with an example ?

 

[dave_59]

A lot depends on how you expect to communicate between SV and SC. See https://verificationacademy.com/cookbook/UvmConnect that shows you how to connect using TLM.

 

[svontop]

A lot depends on how you expect to communicate between SV and SC. See https://verificationacademy.com/cookbook/UvmConnect that shows you how to connect using TLM.

Hi Dave,

Thanks for input.

in My env i am using C++ transactors with SV TB now i want to create SC wrapper is it necessary to use UVM ?

with out using UVM is it possible to create SC wrapper ?

do i need to create ref model in SC or i can use SV TB by calling them in SC test case ?

 

[dave_59]

Anything is possible in software with the right amount of time and money. :-D

When you say you have a SV TB without UVM I don't know what that means.

You can instantiate Verilog/SystemVerilog modules in SystemC modules and the other way around just like Verilog-to-Verilog module instantiations with connections through ports. The UVMConnect uses the SystemVerilog DPI to communicate with C, and C communicates with SystemC. You can either invent something yourself, or look at the open-source code and create something based on it.