SystemC portmap with bit/part select

[ShanghaiDSP]

Hi there,

I'm trying to create a SystemC top level module by instantiating several modules.
The top-level-module has e.g. a sc_uint-type interface with 8bit, the instantiated modules have bool-interfaces. So I create 8 instances and want to connect the bool port of instance 0 to bit zero of the top-level vector port, instance 1 to bit 1 of the vector...and so on.

I want a simmilar thing with sc_uint<128> port of the instances...the top-level module got a 1024 bit sc_uint port.

Here a snip-set from the top-level module:

SC_MODULE(stim_top){
	
	sc_in	<bool> clk_i;
	sc_in	<bool> rst_n_i;
	sc_out	<sc_uint<8> 	        fifo_write_en;
	sc_out 	<sc_uint<8* 128>	fifo_write_data;
...

stim_0.fifo_write_en(fifo_write_en[0]); // bit select
stim_1.fifo_write_en(fifo_write_en[1]); 
...
stim_0.fifo_write_data(lfifo_write_data((1+0)*128-1,0*128)); //part select 
stim_1.fifo_write_data(fifo_write_data((1+1)*128-1,1*128));

The instantiated module:

SC_MODULE(stim){

        sc_in	<bool> clk_i;
	sc_in	<bool> rst_n_i;
	
	sc_out	<sc_bool > 		fifo_write_en;						
	sc_out 	<sc_uint< 128> > 	fifo_write_data;

...

With cadence ncsim its not compiling....it complains:

no instance of overloaded function
          "sc_core::sc_out<T>::operator() [with T=bool]" matches
          the argument list
            argument types are: (
                      sc_core::sc_signal_inout_if<sc_dt::sc_uint<16>> *)
            object type is: sc_core::sc_out<bool>
        stim_1.fifo_write_en(fifo_write_en[0]);

For part select a similar error occurs.
Changing from bool to sc_uint<1> makes also no difference.

Has anyone an idea how to solve this? :?:

Thank you !