SystemC is a modeling library. It is primarily used for high-level systems modeling of hardware. A hardware system typically has many concurrent processes and deals with signals that have formats beyond what most general purpose processors deal with (8,32, and 64-bit data integer and float data).
The main advantage of SystemC is you have the full power of C++ to write high-level of abstraction models with a library of applications and methodologies to handle most applications, especially algorithms that are data-flow dominated . This gives you the performance to do virtual prototyping that many other simulation environments cannot give you.
The main disadvantage of SystemC is you have the full power of C++ to write high-level of abstraction models and all the software debugging issues that come with it. Another disadvantage is that if you need to write low-level, or control-dominated models, you lose all of the performance advantages compared to existing hardware description languages.
That brings us to SystemVerilog, which came about to merge the efforts of several hardware description and verification languages, including Verilog, VHDL, Vera, and others into a single language. Modeling and verifying hardware requires more detailed timing information and access to bit-level data types that is more difficult for higher level languages like C++. You also can get global optimizations, like merging of processes synchronized to a common signal like a clock that you cannot get using a general purpose c++ compiler.
I have always said that it was unfortunate that they chose to include the words "System" and "Verilog" when they named SystemVerilog. It makes it very confusing when trying to distinguish between SystemC and SystemVerilog as they are addressing different target audiences.
Dave