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systemC language Future

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shan14

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Hi

Guys I want to learn systemC . but I am confused between system verilog and systemC which language should I learn??

which language has brighter future or both have equal importance?
 

dave_59

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SystemC is a modeling library. It is primarily used for high-level systems modeling of hardware. A hardware system typically has many concurrent processes and deals with signals that have formats beyond what most general purpose processors deal with (8,32, and 64-bit data integer and float data).

The main advantage of SystemC is you have the full power of C++ to write high-level of abstraction models with a library of applications and methodologies to handle most applications, especially algorithms that are data-flow dominated . This gives you the performance to do virtual prototyping that many other simulation environments cannot give you.

The main disadvantage of SystemC is you have the full power of C++ to write high-level of abstraction models and all the software debugging issues that come with it. Another disadvantage is that if you need to write low-level, or control-dominated models, you lose all of the performance advantages compared to existing hardware description languages.

That brings us to SystemVerilog, which came about to merge the efforts of several hardware description and verification languages, including Verilog, VHDL, Vera, and others into a single language. Modeling and verifying hardware requires more detailed timing information and access to bit-level data types that is more difficult for higher level languages like C++. You also can get global optimizations, like merging of processes synchronized to a common signal like a clock that you cannot get using a general purpose c++ compiler.

I have always said that it was unfortunate that they chose to include the words "System" and "Verilog" when they named SystemVerilog. It makes it very confusing when trying to distinguish between SystemC and SystemVerilog as they are addressing different target audiences.

Dave
 
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mrflibble

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The main advantage of SystemC is you have the full power of C++ to write high-level of abstraction models ...

The main disadvantage of SystemC is you have the full power of C++ to write high-level of abstraction models ...
*grin* Not only amusing, but too true as well.

In addition to Dave's explanation a 100% personal and thus possibly quite random observation...

Some time ago I tried SystemC along the lines of "mmh, lets see what this can do". The experience was so-so. Maybe due to lack of tools/libraries back then, maybe due to expectation value, who knows. Short version is that I didn't really find it to be a big help in modeling and then getting an implementation done. This was before I ever mucked about with SystemVerilog.

Then later I started using SystemVerilog, and with it DPI-C. DPI-C works for both C and C++. All you need to do is give your linker the correct kick and you are good to go. And here I found the mix of SystemVerilog language constructs (especially the constrained random verification bits) in combination with being able to link in your favorite C++ classes was Pretty Darn Handy [tm] in getting things done.

So from my totally personal viewpoint: Forget hearing about SystemC, just use SystemVerilog (and the DPI-C feature) and you are good to go. :)

For a real quick example see this one:
http://www.edaplayground.com/x/3Uh

There's a couple of ways to get it to work, but the "dump it in the C namespace" approach shown in that example is not a bad idea at all.
 
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shan14

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HI

Thanks for your valuable reply
So now I have decided to go for system verilog.
SO what are the pre requisites for learning systemverilog??
I know verilog is must but is C++ also required??
 

TrickyDicky

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Assuming you are trying to design digital systems, you need to learn how digital logic works. If you come into it with a programming head on you are doomed to fail. Code for synthesis is nothing like programming c/c++. Once you've got the hang of digital design, you can move on to verification which is ironically written very much like c++.

So no, no knowledge of c++ is required
 
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mrflibble

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Nope, no C++ required. You only need it when you want to do stuff that is easier to get done in C++ than in SystemVerilog. And I should add that the I only ever used the C++ part for modeling and simulation, not for implementation. That way you can make a working behavioral model with mostly SystemVerilog and a bit of C++ for things that would be too annoying to get done in SV. And the actual implementation is still 100% boring old HDL coding.
 

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