systemC and systemVerilog

[elvishbow_zhl]

systemc dpi pli

Could anybody tell me about the difference and prospect of systemC and systemVerilog. It seems that systemC is supported by Cadence and SystemVerilog by Synopsys. and both are created for system and RTL and verification.

 

[khorram]

transaction level modeling systemverilog systemc

SystemC:
1) based on C++
2) is used for system design
3) is useful in system verification
4) is useful to model a system in transaction level
5) useful for hardware/software co-design and co-verification
6) A subset of C++
7) Implementation simulator (C++ compiler) is freely available
8) Architectural Design and Verification

SystemVerilog:
1) is used for Hardware design
2) is used when we are going to verify block-level designs
3) is a superset of traditional Verilog
4) can be used at RTL and gete level descriptions
5) Adds many features to support verification (e.g. Assertions)
6) adds many features from VHDL that were missing in verilog
7) RTL & Gate level Design and Verification

RGDS
KH

 

[anjali]

uml systemverilog

system C - transaction level modelling
system verilog - signal level modelling

 

[elvishbow_zhl]

By the way,
what is the transaction level definitely means?
As I know in ASIC design flow : there are just
SPEC->BEHAVIOR->RTL->GATE->TRANSISTOR

 

[xworld2008]

Transaction level model is just for verification or simulation, it just is a data control model.
And i like to use systemverilog, because use systemc is a co-simulation ,it need two tools and two language to run. and systemverilog is superset of verilog , so it just one tools and one language, i think this will have little question.

 

[maxsnail]

systemc main benifit leverage from C++ language.
but it is difficult for hw designer to learn.
now cadence add some verifiction library like SCV,CVE,and VIC,
focuse on rtl/chip/block verifiction.
pepole can refer one book named "advaced verfication"
system verilog, currently sysnopsys is the leader.
but now I have not found a cracked license,
hope next year my company will upgrade to 2005.06.sigh....
it is to replace e and vera.

 

[eeeraghu]

SystemC mainly for system level Design, Architecture Description and verification of system level.
System Verilog New features such as assertions and other important features used for design as well as verifiction.

 

[shreeks]

khorram is absolutely right, would like to point out couple of things here.
1. SystemC hasnt been proven good with RTL
2. SystemVerilog avoids PLI bottlenecks to a good extent as compared to SystemC or any HVL. It can increase the simulation speed tremendously. Smooth Interfaces between RTL and Testbenches & even simulator
3. DPI is another feature for SystemVerilog
4. From a programmers point of view SystemC is the best for verification, but SystemVerilog will be the one to stay long

 

[skpatel73]

SystemC is built into a lot of the simulators now, including Modelsim and Aldec. This means no PLI, and no slowdown in runtime.

The C++ leverage for SystemC shouldn't be underestimated. If you were going to write the same verification suite in SystemC and in SystemVerilog, I believe the SystemC version would be much easier and faster to write. Plus, since its native C++, you can incorporate C-models or the like from the systems guys and get much tighter coupling to the intent of the design. And, since its C++, you can give the SW guys examples of working code to build off of, and you can use the stand-alone kernal to interface to a driver and actually use the same verification code to drive emulation and chip validation in the lab. It couples well upstream and downstream. SystemC is hard to learn, and what I've mentioned isn't trivial to do, but its helped us tremendously.

That being said, I do tend to believe that the people using Verilog will end up using SystemVerilog, and the VHDL user will end up using SystemC, so both will co-exist until the next best thing comes along.

Samir

 

[andromeda]

We are Verilog users and we end with SystemC-Verilog cosimulation.
This is true that (for Cadence tools for sure) there is no language-to-language overhead for SystemC-Verilog cosimulation, so whole DPI stuff is not advantage but problem (faster one then PLI, but still ...) for SystemVerilog.
Currently, people are start to use SytemVerilog for verification only, it is not widely used for design yet due to non-complete tool support (even with Synopsys toolset).
In a meantime, SystemC is widely used for arhitecture level modeling and iterations, TLM (transaction level modeling) becomes invaluable part of design flow.
SystemC and SystemVerilog overlap on verification area. Because of verification components reuse through different level of complexity (from block-level to system-level verification) nobody mixes SystemC and SystemVerilog verification on the same project.
My bet is SystemC (not only with VHDL and not only in non-USA). It is simply more open, chip, easier to mix with all C/C++ legacy, ideal for architecture development, hw-sw co-development.
I don't see any advantage SystemVerilog has over SystemC for verification purpose. And if you do everything except RTL code in SystemC, automatic RTL code generation tools already are under development.
What is interesting is usage of UML in whole game ...

 

[skpatel73]

Do you have any links for using UML with SystemC? I haven't heard of any efforts in that regard, but it sounds interesting!

 

[khorram]

Do you have any links for using UML with SystemC? I haven't heard of any efforts in that regard, but it sounds interesting!

What's your application for this link?

RGDS
KH

 

[gabeusse]

there are a couple of articles you might want to download form the web, I tried to upload them but my network didn,t allowed it. their names are:

UML models to SystemC
SystemC code from UML models

they are both on PDF

 

[s8319]

I think the only different is which one is supportted better by the EDA software, if Cadence and Synopsys all declared that SV win, then SV win. But their are competitions, NC prefer SC and vcs prefer SV, so which one is better depend on how they will be supported and popularized