no_mad
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Hi,
I'm new in System Verilog with OOP.
Here is my question.
What's the motivation of "virtual" in SV OOP?
⇒virtual method
⇒virtual class
Can someone please explain this to me.
Why We need "virtual" ??
Please help me out here. Thanks
-no_mad
I'm new in System Verilog with OOP.
Here is my question.
What's the motivation of "virtual" in SV OOP?
⇒virtual method
⇒virtual class
Can someone please explain this to me.
Why We need "virtual" ??
Please help me out here. Thanks
-no_mad