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System Verilog Random Seed Variation

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spartanthewarrior

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verilog random seed

Hi All,

Can any body tell How to vary Seed Value in System Verilog.

I am working on Synopsys VMM Methodology.
 

vinod_cheedella

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systemverilog random seed

srandom(int seed) is the key to have manual seed....

class packet;
rand bit [7:0] header;

function new(int seed);
this.srandom(seed);
endfunction
endclass

initial begin
packet p=new;
p.new(33);
end
 

aji_vlsi

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random seed verilog

spartanthewarrior said:
Hi All,

Can any body tell How to vary Seed Value in System Verilog.

I am working on Synopsys VMM Methodology.

I highly recommend to use:

simv +ntb_random_seed = <val>

One can quickly build a random seed gen in Perl/UNIX.

Ajeetha, CVC
www.noveldv.com
 

raul_777_h

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verilog seed

main() {
time_t *t;
srand(time(t));
printf("%d\n", rand());

exit(0);
}
and compile it use gcc. output named random.
Then use this option:
+vera_random_seed=`./random`
 

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