[SOLVED] System Verilog Projects

[Hrithik Reddy]

Guys,
I need help here, I have to complete a project in SYSTEM VERILOG course but i have no idea in what i should do. I request everyone of you to just suggest me some websites and openwares where i can download simply and easy projects in SYSTEM VERILOG and implement it to pass the subject.
Please guys give me a fast reply.

 

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[RANT]
A fine example of the quality education that is being given to students by money making engineering mills that stress quantity over quality, and pure theory over any practical application of engineering principals. Of course the result being...."i have no idea in what i should do". Of course you don't have any ideas, you've never had to think about what you could do, you've either been told to study a theoretical book, do these problem sets, or do this project with step by step instructions. But to actually apply your knowledge to something useful, without a step by step procedure? No way, why would any engineering school do such a thing...that might mean you would be able to solve an employers problems ... we can't have that happen!

The system is broken and is producing engineers I would never recommend for hiring, and I've done exactly that so many many times after interviewing people that shouldn't even be called an engineer. Many of them have Master's degrees but don't even understand the most basic practical engineering issues. I've met some that can't even tell you what Ohm's Law is. Let alone how to design a mux in VHDL/Verilog after having claimed to be experts at HDL. Sure you can give some of them Matlab and some theoretical problem and they can solve some complex difference equations, but ask them to build that in an FPGA? Forget it. The garbage they will produce will need to be tossed and re-written by someone with a Bachelor's degree that actual thinks like an engineer and not some theoretician.
[/RANT]

So you want an idea for an SV project:
You could simply make a bus transactor model of something like AXI4 or Avalon and put that in an SV testbench along with some IP core that has that bus. Run a bunch of random constrained tests on the IP using your transactor model and collect statistics. Bingo, now you have a SV project, that you did yourself while learning something in the process (instead of plagiarizing) and can pass the subject. Or take the lazy way out and buy a project from one of those "companies" I've read about that cater to the student project mill. :thumbsdown:

 

[Hrithik Reddy]

Thanks for the reply and a great idea to implement using system verilog, but dude the problem is that i don't have enough time or resources to complete the project you in the given deadline set by our faculty. I have to complete it another week. So i have no other option than to give a plagiarized report atleast to pass the subject.
So, i just want some readymade simple project which i can present, so if you know ny sources from where i can get it i would be thankful if you shared it with me.

 

[mrflibble]

So fail the subject and try again later. At least that way you do it on your own and at least learn something. Paying good money to attend some learning institute and then not learning things seems a bit counterproductive to me.

Or if you think this is a viable way of doing things then you should learn how to google for other people's work, since that is what you will be your modus operandi in future working live. ;-)

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Other than that, complaining to your faculty about lack of time & resources is good training. If you get into any engineering job, a good skill is to be able to complain about lack of time & resources ... and then getting more time & resources.

 

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...dude the problem is that i don't have enough time or resources to complete the project you in the given deadline set by our faculty...

Is this the correct translation: I was assigned the project 3 weeks ago, but was too busy partying with some hot chicks to realize that the project deadline was coming up. Of course it's the faculties fault for assigning us the project when there are so many hot chicks that want to party with me. ;-)

I'm with mrflibble, just accept a lower grade or not pass and retake the course. As I see it you either wasted time procrastinating or you don't know the subject well enough and therefore should retake the class.

 

[Ramdas Mozhikunnath M]

Here is a FREE course that teaches basics of SOC Verification and SystemVerilog language which includes a project as well. Try this out if that helps

 

[mrflibble]

Here is a FREE course that teaches basics of SOC Verification and SystemVerilog language which includes a project as well. Try this out if that helps

Looks interesting. Thanks for the tip. I take it you are the author of that course?

 

[Hrithik Reddy]

Thank a lot sir. your reply was way more helpful than the reply given by the previous guy.

 

[mrflibble]

If you really are interested in actually learning things then that udemy link is indeed useful. You should have said you wanted to learn things, instead of saying "gimme stuff I can pawn off as my own work". Another site with lots of systemverilog tutorials is this one: https://www.asic-world.com/systemverilog/tutorial.html

Doulos also has some good stuff: https://www.doulos.com/knowhow/sysverilog/

good luck!