[SOLVED]System Verilog Function Usage

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russeree

Newbie level 2
I am very new to functions, I have a parameter to specify the input freq(mhz). Would this return a value I could use to specify a vector width?
Code:
function int _ms_unit_width;
int freq_mhz = (int_input_freq_mhz/1000);

russeree

russeree

points: 2

russeree

Newbie level 2
I was more concerned about the output type of an int? Is that a legal value to put a 'input wire [x:y] name' declaration?

Super Moderator
Staff member
Verilog and sv aren't strongly typed languaages like VHDL, so you can assign an integer to a wire vector, though you may end up with truncation depending on the value of the integer and the width of the vector.

russeree

points: 2