[SOLVED] System Verilog Function Usage

[russeree]

I am very new to functions, I have a parameter to specify the input freq(mhz). Would this return a value I could use to specify a vector width?

function int _ms_unit_width;
    int freq_mhz = (int_input_freq_mhz/1000);
    _ms_unit_width = ($clog2(freq_mhz)+1);
endfunction

 

[ads-ee]

Using $clog2 is how you do that in Verilog so it should work just as well in SV.

 

[russeree]

I was more concerned about the output type of an int? Is that a legal value to put a 'input wire [x:y] name' declaration?

 

[ads-ee]

Verilog and sv aren't strongly typed languaages like VHDL, so you can assign an integer to a wire vector, though you may end up with truncation depending on the value of the integer and the width of the vector.