I have a testbench code too where I instantiate module test.
Code:
module tb_test();
logic clk,xx;
enum_t test_op;
My question is how do I make the enum_t type available for the testbench. I tried defining it in the testbench file, but there is an error during simulation.
When I dont declare enum_t in the testbench, the error says:
** Error: D:/tb_test.sv(11): 'enum_t' is an unknown type.
Or did you omit the '()' for an instantiation?
Re: system verilog error in modelsim with enum types.
Unfortunately, because the enum label identifiers are declared at the same scope level as the enum type, importing just the enum type does not import the enum labels. So you need to import them explicitly, import enum_types::enum_t;
import enum_types::a;
import enum_types::b;
import enum_types::c;