[System verilog] Difference between task with and without prototype in interface

[maulin sheth]

Hello All,

I am confused for :

1.What is difference between full prototype and w/o prototype for function and task in interface?

2.What is the difference between export in modport for task with prototype and w/o prototype?

Thanks in advance

BR,
Maulin

 

[dave_59]

These are features rarely used in SystemVerilog today. They come from the original Superlog language before Object oriented programming was introduced. The intent was so that if you had two modules connected by an interface, one module could call a task defined in the other module through a series of exports and imports.

Use class objects instead.

 

[maulin sheth]

Hello Dave Rich,

Thanks for help.

I have a doubt for below case :
1)

interface simple_bus (input logic clk); // Define the interface
logic req, gnt;
logic [7:0] addr, data;
logic [1:0] mode;
logic start, rdy;

	modport slave( input req, addr, mode, start, clk,
			output gnt, rdy,
			ref data,
			export Read,Write);
	// export from module that uses the modport

	modport master(input gnt, rdy, clk,
			output req, addr, mode, start,
			ref data,
			import task Read(input logic [7:0] raddr),
			task Write(input logic [7:0] waddr));
	// import requires the full task prototype

endinterface: simple_bus

module memMod(interface a); // Uses just the interface keyword
logic avail;

	task a.Read; // Read method
	avail = 0;
	...
	avail = 1;
	endtask

	task a.Write;
	avail = 0;
	...
	avail = 1;
	endtask
endmodule

module cpuMod(interface b);
enum {read, write} instr;
logic [7:0] raddr;

	always @(posedge b.clk)
	if (instr == read)
		b.Read(raddr); // call the slave method via the interface
		...
	else
		b.Write(raddr);
endmodule

module top;
logic clk = 0;

	simple_bus sb_intf(clk); // Instantiate the interface

	memMod mem(sb_intf.slave); // exports the Read and Write tasks
	cpuMod cpu(sb_intf.master); // imports the Read and Write tasks

endmodule

Doubt is : we have exporting task from slave and import to master. While importing task to master, we have define input logic raddr, so what will pass to raddr as it is not defined in interface or not any return value of export function.

Please help me clear my understanding.

BR,
Maulin Sheth

 

[dave_59]

The example is not correct. The tasks inside module memMod should have declared inputs raddr and waddr. The example that follows shows the task header correctly. The point of this example is to show the tasks initiating transactions using the other signal in the modport to pass data. The tasks themselves do not need pass data through arguments or return values.

This section of the LRM is one of the most poorly documented and reviewed. I doubt any synthesis tool supports it. Like I said earlier, it was was an early attempt at OOP that was abandoned.

 

[maulin sheth]

Hello Dave Sir,

Thank you very much for your help.
Hows it possible such a poorly documented in LRM itself..

So, how data pass from task without any arguments or return values?

Thanks in advance.

--
Thanks & Regards,
Maulin Sheth

 

[dave_59]

A task or function is just a subroutine that can access any of the signals declared inside the module or interface it is declared in. For example, the functions below pass no arguments at all:

module a_module(input wire clk,rst, output var logic [7:0] cnt);

function void reset;
  cnt = 0;
endfunction
function void count;
  cnt <= cnt +1;
endfunction

always_ff @(posedge clk or negedge rst)
  if (!rst)
      reset;
  else
      count;
endmodule