System verilog code output

[sunidrak]

hi all,

How to cheak output of this code in Modelsim, I am not getting any output neither in transcript window nor in wave window ,Please explain how to check this code output


virtual class A ;
virtual task disp ();
$display(" This is class A ");
endtask
endclass

class EA extends A ;
task disp ();
$display(" This is Extended class A ");
endtask
endclass

program main ;
EA my_ea;
A my_a;
initial
begin
my_ea = new();
my_a = my_ea;
my_ea.disp();
my_a.disp();
end
endprogram