mint
Junior Member level 2
Hi All,
I'm currently researching for best techniques, methodology etc to refine a system level design to RTL to gates. What are you guys using? Do system guys develop the system design, functionally verify it and then pass it to RTL guys? At RTL level, do you re implement everything in VHDL, Verilog? How do you ensure that the RTL design match the design intent in the system design? Anybody have experience with this? Thanks.
I'm currently researching for best techniques, methodology etc to refine a system level design to RTL to gates. What are you guys using? Do system guys develop the system design, functionally verify it and then pass it to RTL guys? At RTL level, do you re implement everything in VHDL, Verilog? How do you ensure that the RTL design match the design intent in the system design? Anybody have experience with this? Thanks.
