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There are some HDL which makes the system level design possible. The most known are:
SystemC, SystemVerilog and recently SystemVHDL.
The tools used are Modelsim, Riviera, SystemCrafter, SystemC lib+MSVC++, ....
Hope it help !
Nomarly, the system level verification works with macro cell, but the spice simulator works with a device (real or Idea). However, with some setup, and build a spice macro, you can run at system level by spice simulator but it is very complicated.
Some tools can support for macro cell or device, and that is a good choice for system verification.