For system design, you can find many papers and documents from Google search, say SystemC,
SystemVerilog etc.
For verification, another book I 'd like to suggest is
Wrting testbench, Functional verification of HDL Models. I remember someone had ever posted the
1st edition here.
You can find some resources in cadence home page, search for cadence white paper, u will more information about system design and system level verfication