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System C interfacing to Verilog

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Sep 1, 2008
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systemc verilog


I've been tasked by my supervisor to interface from System C to Verilog.. I have just been introduced to these tools.. So, i am not sure on what exactly I must do to set the infrastructure up..

But basically, i need to simulate a RAM controller (SystemC) to the timing diagrams of Micron's RAM simulation model (Verilog).

Anyone has any elaborative insights about doing so?


systemc dram simulator

Is systemc model is TLM or RTL ??
If TLM you need to write wrappers first.
You need to provide API calls to the systemc model, crate a dll. Integrate in verilog environment and simulate.
I guess you need to use PLI from verilog side.
U need a mixed language simulator, modelsim.

mixed systemc verilog

What is the difference between RTL and TLM?

aistb systemc

TLM is transaction level. there is no pin concept here. Functionality is implemented algorithmically and interfaces are function calls.
I hope you know about RTL.

c to verilog

My long term goal is to look at power consumption.

So, i guess.. RTL would be the appropriate model.. Hence, what aspects of systemC should i consider?

integrating verilog rtl with systemc

Are you going to develop models or interface.
Systemc is meant for system level design. I dont think systemC RTL synthesizer are yet to be proved. I am not sure about analyzing power consumption using systemc models. I read an article long back. It seems possible.

If you already know systemC then only thing you have to learn is how to provide API calls to the models.
I have not actually worked on it.
About integration part I think it will be given in the user manuals of the simulator you are using, if it supports mixed language simulation.

accessing system c models in verilog

I am new to SystemC.. For the moment, i am guessing that i just need to create interfaces in SystemC to link to a known processor simulator..

Do i need the verification library SCV and the TLM downloads?

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