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system and sampling clock for modultor

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amitk3553

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Hello sir/mam,

if buffer size is of 32 bits.Further we are using shift register and this register is actually connected to guassian multipliers.


If data(32 bits) is entered into buffer at positive edge of CLK_IN = 1 Mhz, then clock(SAMPLE_CLK_IN) at which data is entered in shift register or in Guassian filter(32 bits are processed in Gaussian filter one by one) must be 32 times faster than ClK_IN,Is this right approach ?

Or we use SAMPLE_CLK_IN double of CLK_IN(1 Mhz) means 2 Mhz,then How would we synchronise CLK_IN with SAMPLE_CLK_IN??

According to my understanding SAMPLE_CLK_IN should be 32 times( 32Mhz ) if CLK_IN = 1Mhz.Please clarify this.

Please tell me that what would be relative values of CLK_IN, SAMPLE_CLK_IN, SYMBOL_CLK_IN according to u....

PLAESE RESPOND.
THANKS IN ADVANCE.



Regards
Amit Shandilya
DELHI
INDIA
8587833307
 

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