Synthesizing encrypted RTL using Xilinx ISE

[fahum]

Is it possible to synthesize encrypted RTL using Xilinx ISE ?

If yes , what tool should I use for encryption ? is there any tutorial how to do this ?

Thanks

 

[ads-ee]

I recall ISE uses some industry standard IP encryption for their IP, but I don't recall exactly what it was. I do know that there are a number of vendors that encrypt their RTL IP cores so they can be used in Xilinx without releasing their implementation details.

http://forums.xilinx.com/t5/Design-Entry/How-to-encrypt-my-IP-into-SecureIP-like-LogiCORE-IP-in-XPS/td-p/319503

How come it was sooooo easy to find that by typing "xilinx ip encryption" into a google search?

Maybe it's because you didn't even try using google? :thinker:

 

[fahum]

I got through this link before I posted here, but the link provides no good information, so I was hoping I could find something here

 

[mrflibble]

Welll, exactly one trivial google and less than 10 seconds away: **broken link removed**

1735 IP Encryption and Rights Management

As part of its Plug-and-Play IP initiative, Xilinx has adopted the IEEE P1735 encryption standard to ensure interoperability among IP sources, EDA tools, and the IP cores themselves. The IEEE P1735 standard specifies syntaxes for IP encryption and rights management and provides recommendations for integration with design-specification formats described in other standards. It also recommends use models for interoperable tool and hardware flows, which include encryption, encoding algorithms, and encryption key management.

Use of IEEE 1735 for all Xilinx SmartCORE and LogiCORE IP simplifies the task of encryption and rights management for all IP used in a design. That’s the second hallmark of Xilinx Plug-and-Play IP.

So I guess you found it here after all. ;-)