synthesize error: Slice out of range

[yuanqi]

Hi guy, I met an error when I do the synthesis.
Here is the code:
temp2:=temp3(temp3'LOW+to_integer(Shift)+3 DOWNTO temp3'LOW+to_integer(Shift));
temp3 is 8-bits wide, and temp2 4-bits wide. I want temp2 to be a window of temp3, and the signal Shift control the position of that window. shift holds 2-bits only, which just range from 0 to 3. so the range should be fine. But the error says:
Slice out of range.
Slice [-2147483648:-2147483648] is not within range [7:0].
Do you have any ideas about it? Thanks in advance.

 

[FvM]

I think, there is a different violation of VHDL rules, although not complained by the error message. Slices can't have variable ranges. To achieve what you want to do, you can copy individual bits in a loop like shown below:

FOR I IN 3 DOWNTO 0 LOOP
  temp2(I) := temp3(I+to_integer(Shift));
END LOOP;

 

[yuanqi]

Thanks for your quick reply.
To test the possibility of shifted window structure, I write a very simple code as:

and it is synthesis-able. The only difference I can tell is I use 0 instead of temp3'LOW. But the range of temp3 is [7 downto 0]. Quite confused right now!
Anyway, your approach should work. Thanks again.