Synthesize And gate instead of LUT

[eng.fedail]

Hello all,
Down is part of my ode

variable counter : Integer RANGE 0 to 7 := 0;

if (counter = 7) then
valid <= '1';
end if;

After Synthesize the if condition the result is about LUT to output one at valid signal, I'd like to use and gate instead of that, any idea? I have tried to implement signal instead of variable but I couldn't cause of the Index and the Boolean condition.

thanks

 

[FvM]

The question doesn't seem to make sense. If you are synthesizing the logic for a specific device, the compiler will use the logic elements available for it, may be LUT (FPGA) or macro cells (CPLD). Which device do you expect to provide LUTs and AND gates alternatively?

 

[eng.fedail]

The question doesn't seem to make sense. If you are synthesizing the logic for a specific device, the compiler will use the logic elements available for it, may be LUT (FPGA) or macro cells (CPLD). Which device do you expect to provide LUTs and AND gates alternatively?

The question and your answer for me make sens, Cause I understand now it's related to the device while I was thinking I can build up gates in FPGA

thanks