Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Synthesizable designs - wired (and/or) logic

Thread starter reninroy
Start date Dec 15, 2009

Status: Not open for further replies.

Dec 15, 2009

#1

R

reninroy

Junior Member level 1

Synthesizable designs

Where i can use the wired (and/or) logic? is this logics are synthesizable in verilog HDL?

Dec 15, 2009

#2

RBB

Full Member level 5

Synthesizable designs

Wire ands/ors aren't (or shouldn't) be synthesizable.

Status: Not open for further replies.

Similar threads

G
Watchdog timers and FPGA designs
- Started by gahelton
- Nov 25, 2023
- Replies: 3
PLD, SPLD, GAL, CPLD, FPGA Design
M
Why do digital designs often need multiple clock domains?
- Started by matrixofdynamism
- Aug 3, 2023
- Replies: 3
PLD, SPLD, GAL, CPLD, FPGA Design
P
Implement carrier detection logic in FPGA
- Started by pulkit.vlsi
- Dec 26, 2022
- Replies: 5
PLD, SPLD, GAL, CPLD, FPGA Design
A
sodimm or discrete memory for FPGA
- Started by aminpix
- Jul 20, 2023
- Replies: 1
PLD, SPLD, GAL, CPLD, FPGA Design
L
Image Encryption and Decryption using VHDL
- Started by Lightning89
- Feb 14, 2024
- Replies: 0
PLD, SPLD, GAL, CPLD, FPGA Design

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.

Accept Learn more…

Top