Synthesizable Character in VHDL

[Junus2012]

Dear friends

I am writing a code for transferring characters to the LCD of an FPGA using VHDL. because the char is not Synthesizable I am transferring the code in binary of each char i want to show on LCD. this process is hard and promote to error.

Therefore I would like to ask you if there is other way to send the char directly to the output

I would appreciate your help in advance
Regards

 

[FvM]

I don't understand what's the exact problem.

Character is an enumeration type, but it's synthesizable as other enumeration types or e.g. integer. Some tools will also synthesize character for top entity ports as bit vector with a size of 8 according to the character range. But if your tool doesn't or you want direct access to individual character bits, you can convert a character signal to it's ascii code representation by using a 'pos attribute.

 

[Junus2012]

Dear FvM,

Thank you for your help,

suppose I want to write "VHDL" to the LCD connected to FPGA board, as you know I need to make state machine and send 'v' then 'H' then 'd' then 'L',

suppose the data bus of the LCD is connected to port q on the FPGA, where q is bit vector (7 downto 0)

can I use this ?? q <= 'V' , is it acceptable to send the char in this way ?, cause I read that Char is only used for comparesion ,

thank you onc eagain

 

[TrickyDicky]

if you wanted to use a char, you would need to send:

q <= std_logic_vector( to_unsigned( character'pos('V'), q'length));

Character is an enumerated type, and hence has not binary value. This does the conversion from the enumerated type to binary.