synthesizability of casex and caxez

[ASIC_int]

Is caxex and casez synthesizable?

 

[ckshivaram]

Both casex and casez are synthesizable. Casex generates a don't-care space for unspecified state points. Casez uses a "Z logic value" to represent a don't-care bits.

There are two meanings to an "X". For a simulation, "X" means dont-know but for a synthesis "X" means a don't care. X is synthesizable because it could be anything. All X means it is 1 or a 0.
The statement of a "Z" not being synthesizable is also incorrect. What do you think this verilog code reveals . .
tri [0:3] buf_out = en? in: 4'bz;

Ta-Da! A 4-bit tri-state bus that goes "Z" when disabled.


my knowledge is very limited in this... we can wait for other experts comment too.....

 

[FvM]

I'm using Verilog language only occasionally and never used casex or casez in a design.

To answer the question exactly, I would like to refer to the Synopsys HDL compiler for Verilog manual. It clarifies, that casex and casez are supported. This means, that 'x' respectively 'z' are allowed for case items. The respective bits are simply ignored for the comparison, you can't check the case expression for 'x' or 'z'.

I only see a purpose of casex or casez in simulation, where variables can acutally take respective values. Support in synthesis mainly means, that they can be compiled without error. In addition, you can use the construct to specify don't care conditions, as mentioned by ckshivaram.

 

[ASIC_int]

Hi Fvm:

CAN U PLEASE ATTACH THE DOCUMENT OF Synopsys HDL compiler for Verilog manual? How to get that?

What do u mean by "The respective bits are simply ignored for the comparison, you can't check the case expression for 'x' or 'z'" ?

I have a IEEE document that indirectly say caxes and casez are not synthesizable if caxe expressions have x or z in them.

 

[keith1200rs]

Posts deleted. Please, no pointless arguing or I shall close this thread.

This is FvM's link

Keith.

 

[lostinxlation]

What do u mean by "The respective bits are simply ignored for the comparison, you can't check the case expression for 'x' or 'z'" ?

Have you ever stopped and thought about what kind of logic the synthesis tool will make if 'z' or 'x' are involved in the synthesis ?
It's not a rocket science to understand how z or x in casex/z would be treated during synthesis if you take a real life logic circuit into consideration.