Synthesising a design without inputs and outputs

[BartlebyScrivener]

I am trying to test an on-chip interconnection network I have designed, without the network actually connecting to anything other than itself.

I created a module to instantiate the network.

`include "ENoC_Config.sv"

module synthesis_wrap

 (input logic clk, reset_n);
  
         packet_t [0:(`X_NODES*`Y_NODES)-1] i_data;
         logic    [0:(`X_NODES*`Y_NODES)-1] i_data_val;
         logic    [0:(`X_NODES*`Y_NODES)-1] o_en;
         
         packet_t [0:(`X_NODES*`Y_NODES)-1] o_data;
         logic    [0:(`X_NODES*`Y_NODES)-1] o_data_val;
         logic    [0:(`X_NODES*`Y_NODES)-1] i_en;
         
  ENoC_Network
    inst_ENoC_Network (.clk(clk),
                       .reset_n(reset_n),
                       .i_data(i_data),
                       .i_data_val(i_data_val),
                       .o_en(o_en),
                       .o_data(o_data),
                       .o_data_val(o_data_val),
                       .i_en(i_en));
endmodule

The network code works in simulation, but when I synthesize in Quartus, I get a warning that no clocks are defined. I am guessing it literally cancels out all my code because without input and output nodes, it does nothing.

How could I get round this? i.e is it possible to tell Quartus to treat the values of i_data, i_data_val and i_en as if they might change, and o_data, o_data_val, and o_en as if they were connected to something?

 

[FvM]

A synthesis tool is pretty good in removing meaningless logic.

You might be able to keep registers and logic cells with no fanout by synthesis attributes. This is the usual way to create logically redundant structures like logic cell delay chains. But I never tried for a design with no outputs at all.

 

[BartlebyScrivener]

A synthesis tool is pretty good in removing meaningless logic.

You might be able to keep registers and logic cells with no fanout by synthesis attributes. This is the usual way to create logically redundant structures like logic cell delay chains. But I never tried for a design with no outputs at all.

Thanks FvM, I found attributes googling and have tried using noprune on the simulated output registers, and preserve on the simulated input registers, to no avail. Still removes all logic.

module synthesis_wrap

 (input logic clk, reset_n);
  
logic    [0:(`X_NODES*`Y_NODES)-1] i_data /* synthesis preserve */;
logic    [0:(`X_NODES*`Y_NODES)-1] i_data_val /* synthesis preserve */;
logic    [0:(`X_NODES*`Y_NODES)-1] o_en /* synthesis noprune */;
        
logic    [0:(`X_NODES*`Y_NODES)-1] o_data /* synthesis noprune */;
logic    [0:(`X_NODES*`Y_NODES)-1] o_data_val /* synthesis noprune */;
logic    [0:(`X_NODES*`Y_NODES)-1] i_en /* synthesis preserve */;
       
  ENoC_Network
    inst_ENoC_Network (.clk(clk),
                       .reset_n(reset_n),
                       .i_data(i_data),
                       .i_data_val(I_data_val),
                       .o_en(o_en),
                       .o_data(o_data),
                       .o_data_val(o_data_val),
                       .i_en(1'b1));
endmodule

It seems crazy that you cannot synthesize a module from a larger design on its own to get area/timing estimates etc.

 

[FvM]

It seems crazy that you cannot synthesize a module from a larger design on its own to get area/timing estimates etc.

By nature, a resonable module has in- and outputs. What's against exposing them to the outer world?

Virtual pins might work as dummy connection for the signals.

 

[BartlebyScrivener]

The network does have inputs and outputs, its just that these would be connected to other modules within the fpga. I could be wrong but, I am concerned that if I expose the pins to the outer world, there will a) be too many for the design to fit on an FPGA and b) Warp my results for area and speed.

I will look up virtual pins thanks.

- - - Updated - - -

Virtual pins looks like what I need, except I need a licence for that function! Oh well, thanks for your help.