In fact, the order of evaluation matters for a few cases, where blocking assignments are made in one always block and the result is used in the other. Although synthesized hardware doesn't work sequentially (or has a hardware equivalent of a blocking assignments), the evaluation oder of the behavioral description affects the synthesis result. The simple rule is to avoid all constructs that have unpredictable results related to unknown evaluation order.
But the problem is clearly stated in the Verilog specification and many text books, I don't see any source of doubt in this regard.