synthesis tool evaluation of multiple always blocks.

[ASIC_int]

Does synthesis tool evaluate the always blocks one after another instead of concurrently if there are more than one always block in one module?

 

[lostinxlation]

What difference do synthesis tools make by "evaluating" always' sequentially or concurrently ? A synthesis is not a simulation.

 

[ASIC_int]

But an RTL goes for simulation as well as synthesis. Synthesis output may depend on sequential and concurrent evaluation of always blocks.

 

[FvM]

In fact, the order of evaluation matters for a few cases, where blocking assignments are made in one always block and the result is used in the other. Although synthesized hardware doesn't work sequentially (or has a hardware equivalent of a blocking assignments), the evaluation oder of the behavioral description affects the synthesis result. The simple rule is to avoid all constructs that have unpredictable results related to unknown evaluation order.

But the problem is clearly stated in the Verilog specification and many text books, I don't see any source of doubt in this regard.