In the code above 'x' is defined to be a one dimensional array, so 'x' only has one index. What you defined for IN_FRAME is a three dimensional array which will require specifying three indices: IN_FRAME : generic_3d_array ( 0 to ROWS_PER_FRAME - 1 , 0 to PIXELS_PER_ROW - 1 , BITS_PER_PIXEL - 1 downto 0 ) ;K-J,
In #15 you wrote:
Assume the following code:
Code:signal x is array ( 0 to 2 ) of std_logic_vector ( 7 downto 0 ) ; signal y : std_logic_vector ( 7 downto 0 ) ; y <= x ( 1 ) ;
Despite the fact that I left off the second boundary of x - the above will be legal.
How is it any different than:
?Code:row <= IN_FRAME ( some_row_number ) ;
But if IN_FRAME is defined as:IN_FRAME is a three dimensional array which will require specifying three indices
IN_FRAME : generic_3d_array ( 0 to ROWS_PER_FRAME - 1 , 0 to PIXELS_PER_ROW - 1 , BITS_PER_PIXEL - 1 downto 0 ) ;
and when addressing an element you specify 3 indices - won't the result be a single bit std_logic ??
std_logic == IN_FRAME ( 1 , 2 , 3 )
I want to define IN_FRAME in such a way that I'll be able to:What are you actually trying to do?
I want to define IN_FRAME in such a way that I'll be able to:
1. Address specific rows,
2. Address specific pixels.
Thanks Kevin,You can do what you want either as an array of pixels or as a multi-dimensional array as has been discussed.
-- The following custom types will be defined in an external package.
type generic_1d_array ( natural range < > ) of std_logic_vector ;
type generic_2d_array ( natural range < > , natural range < > ) of std_logic_vector ;
-- I have an entity input:
IN_ROW : generic_1d_array ( 0 to PIXELS_PER_ROW - 1 ) ( BITS_PER_PIXEL - 1 downto 0 ) ;
-- I want to create indexed delayed copies of IN_ROW ( essentially an array of rows - with the indexed value indicating the number of delay stages ).
signal row_array : generic_2d_array ( 0 to NUMBER_OF_ROWS - 1 , 0 to PIXELS_PER_ROW - 1 ) ( BITS_PER_PIXEL - 1 downto 0 ) ;
row_array ( 0 ) <= IN_ROW ;
process ( clock ) is
begin
if rising_edge ( clock ) then
for index in 0 to NUMBER_OF_ROWS - 2
loop
row_array( index + 1 ) <= row_array( index ) ;
end loop ;
end if ;
end process ;
-- I define another array:
signal pixel_array : generic_1d_array ( 0 to NUMBER_OF_ROWS - 1 ) ( BITS_PER_PIXEL - 1 downto 0 ) ;
-- At this point - I want to map [U]some[/U] of the pixel elements of [B]row_array[/B] into pixel elements of [B]pixel_array[/B].
-- I write "some" because row_array will have more pixel elements than pixel_array.
pixel_array ( some_pixel_number ) <= row_array ( some_row_number , some_pixel_number_inside_a_row ) ;
library ieee;
use ieee.std_logic_1164.all;
entity test2008 is
end entity;
architecture test of test2008 is
signal clock : std_logic;
type row_t is array(natural range <>) of std_logic_vector; --wouldnt this make more sense to be an unsigned or signed if you're doing pixel arithmatic?
type row_array_t is array(natural range <>) of row_t;
signal row_array : row_array_t(0 to 7)(0 to 7)(7 downto 0);
signal pel_array : row_t(0 to 3)(7 downto 0);
begin
process(clock)
begin
for i in 0 to 5 loop
row_array(i+1) <= row_array(i);
end loop;
end process;
pel_array <= row_array(6)(3 to 6);
end architecture;
Sure.How long are your rows? If you are intended to shift entire rows in the FPGA then your logic use is going to explode very quickly.
Good point. It should be the same type as the input port of the FPGA's DSP block.wouldn't this make more sense to be an unsigned or signed if you're doing pixel arithmetic?
pel_array <= row_array(6)(3 to 6);
Can you show an example of how to do what I want in 1d ?In that case, do what you wish - 2d or 1d. But given the ease of slicing if you need it 1d may be more beneficial.
If VHDL-2008 is not an option and you need unconstrained vector sizes.If you can abstract into higher dimensions by declaring 1d arrays of -> 1d arrays of -> 1d arrays of etc...
In what situation would you bother using true 2D+ arrays?
A "large amount" of FFs is kind of my goal here...You'll be creating a large number of FF and possibly muxes without much effort.
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