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Synthesis tool can bring some functional errors in netlist. For example, DC ultra can translate some logic into wrong gates. You better use logic equivalent check tool to make sure RTL==netlist.
Like Jackson said, glitch can make RTL sim different with netlist sim
Nandigits provides a good netlist debug tool, GOF.
It's very powerful in isolating failing logic in formality check.
For example, starting from one failing cell, using mouse to click on the cell's input pins or output pins, a circuit is drawn. And it makes thing simple for you to check what's wrong in the logic.
Take a look at following link http://www.nandigits.com/p40.htm