synthesis result functional error

[quake]

hi, what usually cause the functional error of the sythesized netlist? I mean the most common reason, like clock, reset or even pads can cause this problem? any others? thanks

 

[jackson_peng]

glitch, especially on your generated clock or reset
metastablity, data exchange between different clock domain.

 

[Nandy]

Synthesis tool can bring some functional errors in netlist. For example, DC ultra can translate some logic into wrong gates. You better use logic equivalent check tool to make sure RTL==netlist.
Like Jackson said, glitch can make RTL sim different with netlist sim

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.

 

[anjali]

async logic should be taken care while synthesis.

 

[quake]

thank you so much. Then the question becomes: what steps are usually done
to find out where the problem is ? since it is so hard to trace those signals in a netlist, any special routines to do it?

 

[xworld2008]

I think you can use formal tools to check you netlist , which can find different between netlist and rtl code.

 

[Nandy]

Nandigits provides a good netlist debug tool, GOF.
It's very powerful in isolating failing logic in formality check.
For example, starting from one failing cell, using mouse to click on the cell's input pins or output pins, a circuit is drawn. And it makes thing simple for you to check what's wrong in the logic.
Take a look at following link
https://www.nandigits.com/p40.htm

GOF is free for none-commercial usage.

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.