[Synthesis] re-balancing/re-timing of registers -> what are pitfalls?

ivlsi · Nov 3, 2012

Hi All,

I've heard that re-balancing of the logic among flops/registers is a complicated task. Could somebody tell me why?

Besides applying relevant commands during Logic Synthesis, what other pitfalls do exist?

Thank you!

oratie · Nov 6, 2012

The big problem of formal verivication. Because, such tool (like Mentor FromalPro or Synopsys Formality) compares input logic for each register between RTL and gate-level netlist. If you asked Synthesis to re-balance logic, the input logic for some registers will be different. For Synopsys Formality, you can use side-file .svf, which is generated by DesignComiler and help Formality to verify such design. Still, it is complicated for tools to verify re-balanced (re-timed) designs.

[Synthesis] re-balancing/re-timing of registers -> what are pitfalls?

ivlsi

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oratie

Full Member level 6

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[Synthesis] re-balancing/re-timing of registers -> what are pitfalls?

ivlsi

Advanced Member level 3

oratie

Full Member level 6

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