Synthesis problem on Synplicity

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OvErFlO

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The problem is : when I make a simulation I can't find ports on my synthetized project, it's possible set a net or a port to it become not synthesizable???

thanks
 

Hi OvErFlO,

Yes. Most of the synthesize tool have this ability. You can add some directive in your

RTL code to do this, please refer the synpl1fy reference manaual for more detail.
 

Have you any idea ???


thanks...
 

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