Synthesis problem on Synplicity

[OvErFlO]

The problem is : when I make a simulation I can't find ports on my synthetized project, it's possible set a net or a port to it become not synthesizable???

thanks

 

[wadaye]

Hi OvErFlO,

Yes. Most of the synthesize tool have this ability. You can add some directive in your

RTL code to do this, please refer the synpl1fy reference manaual for more detail.

 

[OvErFlO]

Have you any idea ???


thanks...