altair_06
Member level 1
HI ,
I am using Xilinx XST to synthesize my module. When i set my optimization goal to speed i am able to obtain reduced number of slices and higher Fmax and when i used area for optimization the number of slices got increased and there was a reduction in Fmax. Reduction in Fmax is agreeable as the optimization is with respect to area, but why did the number of slices got increased. Can anyone give me the reason behind it or is there a mistake in my side.
I am using Xilinx XST to synthesize my module. When i set my optimization goal to speed i am able to obtain reduced number of slices and higher Fmax and when i used area for optimization the number of slices got increased and there was a reduction in Fmax. Reduction in Fmax is agreeable as the optimization is with respect to area, but why did the number of slices got increased. Can anyone give me the reason behind it or is there a mistake in my side.