synthesis of the two rtl

[sun_ray]

The following rtl with always block synthesizes to a D-Flip flop

always @ (posedge clk or nededge rst)
if (rst)
q<= 1'b0;
else
q <= d;

The @ symbol mean whenever the event matches, statements following @ will be executed. Why will the following rtl without the always block not synthesize to a D flipflop then? What will the following rtl then synthesize to?

@ (posedge clk or negedge rst)
if (rst)
q<= 1'b0;
else
q<=d;

 

[rahul.achates]

all statement inside always block will executed on the event match , but if you do not provide always block , means execution will happen one time only , and all statement after that event will executed.

I think @( ) .. is used for modeling purpose or in verification , but if you synthesize @ () , then tool will assign some constant value .. I am not sure if that is synthesizable at all or not !!

Rahul

 

[sun_ray]

all statement inside always block will executed on the event match , but if you do not provide always block , means execution will happen one time only , and all statement after that event will executed.

But @ is a symbol which also signifies whenever there an event the statements following @ will be executed. So @ is also happen whenever there is event just like the always block which allow statements following it to be executed whenever there is an event as you stated. So it is not answering the query in post number 1.

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I think @( ) .. is used for modeling purpose or in verification , but if you synthesize @ () , then tool will assign some constant value .. I am not sure if that is synthesizable at all or not !!

Rahul

Why will @ not synthesizable if If alwyas @ is synthesizable?

 

[rahul.achates]

there is difference -

always @(event1) begin
end


@(event) begin
end


always @(event1)



@(event)


there is difference in all 4 statement ,

1st statement
always@(event1) begin
end


whenever event1 happen, all statement in always block ( inside begin ..... end) will be executed.

2nd statement
@(event1) begin
end

whenever this statement executed, simulator will wait for event1 , once event1 there then simulator will executed rest of statement ....

to keep this statement executed all time, you need to write below code

forever begin
@(event1) begin
end
end

3rd statement ... is similar to 1st statement , except statement just after always @(event1) will executed everytime whenever event1 happen ,

4th statement is similar to 2nd statement , except statement just after @(event1) will be executed , rest will not.

 

[sureshaa]

Guys.. When I give without always, it is showing error " Syntax error near "@"." Are you sure it will synthesis?
If it is yes can u provide full architecture

 

[rahul.achates]

Guys.. When I give without always, it is showing error " Syntax error near "@"." Are you sure it will synthesis?
If it is yes can u provide full architecture

That's why I was saying "@" withput always may not be synthesizable, this is used in modelling or in verification env, this is a event wait statement and synthesis tool doesn;t understand when to execute.

Rahul

 

[sun_ray]

there is difference -
2nd statement
@(event1) begin
end

whenever this statement executed, simulator will wait for event1 , once event1 there then simulator will executed rest of statement ....

to keep this statement executed all time, you need to write below code

forever begin
@(event1) begin
end
end

According to Verilog LRM @ is a symbol that executes WHENEVER the event following it happens. So according to LRM @ should be executed for ever and hence the following should execute for ever. How are you saying it should not happen for ever? I am going by the LRM of Verilog.


2nd statement
@(event1) begin
end

 

[rahul.achates]

According to Verilog LRM @ is a symbol that executes WHENEVER the event following it happens. So according to LRM @ should be executed for ever and hence the following should execute for ever. How are you saying it should not happen for ever? I am going by the LRM of Verilog.


2nd statement
@(event1) begin
end

LRM saying correctly. I have no doubt in that.


what will be the output of below statement -

module temp ;

int i =1 ;
int j = 5;
int clk = 0;

always #5 clk = ~clk;

initial begin

@ (posedge clk) begin
$display(" i = %d" , i) ;
$display("j = %d", j);
end

end

always @(posedge clk) begin
i = i +1 ;
j = j +1 ;
end

initial begin
#200;
end

Can someone simulate this and put results here ?

Rahul

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Please copy paste the output after simulation ...

Thanks

 

[sun_ray]

LRM saying correctly. I have no doubt in that.


what will be the output of below statement -

module temp ;

int i =1 ;
int j = 5;
int clk = 0;

always #5 clk = ~clk;

initial begin

@ (posedge clk) begin
$display(" i = %d" , i) ;
$display("j = %d", j);
end

end

always @(posedge clk) begin
i = i +1 ;
j = j +1 ;
end

initial begin
#200;
end

Can someone simulate this and put results here ?

Rahul

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Please copy paste the output after simulation ...

Thanks

If simulated @ may be executed once , but always @ may be executed for ever. Why does the LRM states then, that @ is executed WHENEVER there is a change in event? So @ should be executed whenever there is a change in the event irrespective of number of times it needs to execute @. Is not it?

Regards

 

[rahul.achates]

If simulated @ may be executed once , but always @ may be executed for ever. Why does the LRM states then, that @ is executed WHENEVER there is a change in event? So @ should be executed whenever there is a change in the event irrespective of number of times it needs to execute @. Is not it?

Regards

It's really depends on where you are using it.

@() .. is event execution ... and I am also saying whenever event happen it will executes but that doesn't mean it will executes forever ... here whenever mean "1st time " ..

I can give you an example --


@ ( posedge signal_A) ;
done something ....



simulator will wait for this even and "WHENEVER" this event happen, below statement will executed ..

hope this will clear your doubts ..

Rahul J