Synthesis issue

[manasic]

Hello All;

I have code which compare two address(which is a std_logic_vector). I have written it in a pacakge named distance with the function named as path_cost. The code is in vhdl and synthesis tool is synopsys 2011.
Below is the code and synthesis error.

package body distance is

  -- purpose: calculate the path cost (distance) between node1 and node2
  -- example: address1 = "234", address2 = "235";
  -- example: closest common ancestor = "230", remainder1 = "4", remainder2 = "5", remainder_width = 1
  function path_cost (

    constant address1 : std_logic_vector (8 downto 0);
    constant address2 : std_logic_vector (8 downto 0))
    return integer is

    variable digit_pointer       : integer := 3;  --the iterator of octal digits
    variable ancestor_identified : boolean := false;
    -- a flag: initialized as false, set to true as soon as the common ancester is identified
    variable remainder_width     : integer := 0;
    variable node_distance       : integer := 0;  -- the distance of node1 and node2

  begin  -- path_cost

    --stage1: find closest common ancestor
    while (ancestor_identified = false and digit_pointer /= 0) loop
  [B] if address1 ((digit_pointer*3-1) downto ((digit_pointer-1)*3)) = address2 ((digit_pointer*3-1) downto ((digit_pointer-1)*3)) then[/B]
        digit_pointer := digit_pointer - 1;  --ancestor unidentified, keep searching
      else
        ancestor_identified := true;
      end if;
    end loop;  --now digit_pointer = remainder_width
    remainder_width := digit_pointer;

synthesis error:

Loading vhdl files: '/net/grads/mchoudha/vhdl/mroots-routing/distance.vhd' '/net/grads/mchoudha/vhdl/mroots-routing/router.vhd'
Running PRESTO HDLC
Compiling Package Declaration DISTANCE
Compiling Package Body DISTANCE
Compiling Entity Declaration ROUTER
Compiling Architecture BEHAVIOR of ROUTER
Warning: /net/grads/vhdl/mroots-routing/router.vhd:18: The architecture behavior has already been analyzed. It is being replaced. (VHD-4)
Warning: /net/grads/vhdl/mroots-routing/router.vhd:27: The initial value for signal 'node_database' is not supported for synthesis. Presto ignores it. (ELAB-130)
Warning: /net/grads/vhdl/mroots-routing/router.vhd:59: 'node_database[0]' is being read, but does not appear in the sensitivity list of the block. (ELAB-292)
Error: /net/grads/vhdl/mroots-routing/distance.vhd:35: Constant value required. (ELAB-922)
*** Presto compilation terminated with 1 errors. ***
Error: Can't read 'vhdl' files '/net/grads/vhdl/mroots-routing/distance.vhd', '/net/grads/mchoudha/vhdl/mroots-routing/router.vhd'. (UID-9)
No designs were read
design_vision>

the code highlighted is giving error. I tried to look for online on this and found that , if loop cannot have a variable value. I am nota ble to change it to fixed values beacuse design needs to flexible. Can anyone suggest a work around. I am waiting for the answer. Will be really great if anyone can help.

Manasi

 

[ads-ee]

Re: Synthesis issue- code not synthesizable

The code you posted doesn't match the router.vhd file. It's not even the complete distance package file.

 

[manasic]

Re: Synthesis issue- code not synthesizable

I have no issue with router.vhd. I have just posted the part of package , which is giving error.

Thanks,
Manasi

 

[rca]

Re: Synthesis issue- code not synthesizable

Hi,
what is at the line 35 in your package where the tool complains?
Regars,

 

[ads-ee]

Re: Synthesis issue- code not synthesizable

Warning: /net/grads/vhdl/mroots-routing/router.vhd:18: The architecture behavior has already been analyzed. It is being replaced. (VHD-4)

So having multiple architectures, behavior, for the same entity is okay with you, since only the last one compiled is the one you really want to use.

Warning: /net/grads/vhdl/mroots-routing/router.vhd:27: The initial value for signal 'node_database' is not supported for synthesis. Presto ignores it. (ELAB-130)

I guess you don't want to use the design in synthesis, I suppose that's okay too if you don't like making anything useful.

Warning: /net/grads/vhdl/mroots-routing/router.vhd:59: 'node_database[0]' is being read, but does not appear in the sensitivity list of the block. (ELAB-292)

I suppose that not having logic that synthesizes the same as it simulates is okay, since you don't want to actually implement it.

Error: /net/grads/vhdl/mroots-routing/distance.vhd:35: Constant value required. (ELAB-922)

I get to line 28 in the posted code and between line 29-35 I'll just have to guess what the code looks like. Line 35 doesn't use a constant value. Problem solved.

 

[FvM]

Re: Synthesis issue- code not synthesizable

  if address1 ((digit_pointer*3-1) downto ((digit_pointer-1)*3)) = address2 ((digit_pointer*3-1) downto ((digit_pointer-1)*3)) then

A slice is expected to a have constant range. As a workaround you can use a bitwise compare in a for loop.

 

[manasic]

Re: Synthesis issue- code not synthesizable

Thanks all;

I got the issue resolved. The problem was that synopsis was not able to synthesis anything for a variable if statement. I opened the loop making it static and removing the variable components from the code. This helped the synopsis to generate comparators for the corresponding if loops. The issues was just related to synthesis. The waveform representation was working good.

Thanks for the help.