synthesis generating different VHDL type than declared type

Hi all:

I am synthesizing a master interface. After synthesis the netlist has a STD_ULOGIC type defined like this

type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
attribute ENUM_ENCODING of std_ulogic : type is "U D 0 1 Z D 0 1 D";
subtype std_logic_2 is std_ulogic range 'U' to '-' ;
type std_logic_vector_2 is array (INTEGER range <>) of std_logic_2;
subtype data_size_2 is std_logic_vector_2 (7 downto 0);

But In my code there is no std_ulogic type.In synthesis script I am using compile_ultra command to compile and before writing netlist , I am using change_names -rules vhdl. Does anyone has any clue about this?

I am facing mismatch problems cause of this..
in my original code i have declared data_size is std_logic_vector (7 downto 0);

Why does it change it??( if i remove change_names command it does not change it)
Also the warning i get is type VHDL-10.

Thanks in advance