synthesis error in ISE

[ya_montazar]

hi,
I want to synthesize a VHDL code by ISE ,but it generated an error:
"Signal to_uart cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release."

	process(rx_ready , start_frame_tmp)
		variable i : integer range 10 downto 0 := 0;
	begin
		i_sig <= conv_std_logic_vector(i,4);
			case i is
				when 0 =>
					start_frame_tmp <= '1';
					end_frame_tmp <= '0';
				when 9 =>
					start_frame_tmp <= '0';
					end_frame_tmp <= '1';
				when others =>
					start_frame_tmp <= '0';
					end_frame_tmp <= '0';
			end case;
			if(start_frame_tmp = '1')then
				to_uart <= character_pos( data_tmp(0) );
			end if;
			if(rising_edge(rx_ready))then
				if(i /= 9)then
					i := i + 1;
					to_uart <= character_pos( data_tmp(i) );
				else
					i := 0;
				end if;
		end if;
	end process;

what's wrong with it???:roll:

 

[TrickyDicky]

the if rising_edge(clk) should surround the whole code, not just part of it.

 

[Basu_Gouda]

variable i : integer range 10 downto 0 := 0

I think you have initialized the signal to_uart like you did in the above variable i. What i meant to say is you cannot synthesize the code if you have initialized any variable with some predefined value do check for this

 

[ya_montazar]

my problem is that the codes before the rising_edge(rx_ready) and in process generates the first edge and make the if rising_edge(rx_ready) expression true;
rx_ready is a signal which comes from another module as a feedback. without this process function the rx_ready do not change and without rx_ready changing the process can not perform?
what solution do you suggest???

 

[TrickyDicky]

variable i : integer range 10 downto 0 := 0

I think you have initialized the signal to_uart like you did in the above variable i. What i meant to say is you cannot synthesize the code if you have initialized any variable with some predefined value do check for this

This is nothing to do with the error

 

[ya_montazar]

variable i : integer range 10 downto 0 := 0

I think you have initialized the signal to_uart like you did in the above variable i. What i meant to say is you cannot synthesize the code if you have initialized any variable with some predefined value do check for this

no, "to_uart" have not initialized...

 

[TrickyDicky]

my problem is that the codes before the rising_edge(rx_ready) and in process generates the first edge and make the if rising_edge(rx_ready) expression true;
rx_ready is a signal which comes from another module as a feedback. without this process function the rx_ready do not change and without rx_ready changing the process can not perform?
what solution do you suggest???

In a syncronous process, you should not have anything outside the clock branch other than an async reset.
You need to think about the logic, and then write the code. Do not just write the code like software.

If you need an initial value, why not just initialise or reset to_uart as a specific value?

 

[imbichie]

You can make the rx_ready as the clock, (means you can use the "rising_edge(rx_ready)") and you can include the assignments under the rising_edge(rx_ready).
So the rising_edge of the rx_ready changes the "i" value and the remaining things also will change.

 

[TrickyDicky]

You can make the rx_ready as the clock, (means you can use the "rising_edge(rx_ready)") and you can include the assignments under the rising_edge(rx_ready).
So the rising_edge of the rx_ready changes the "i" value and the remaining things also will change.

I wouldnt do this. Using things other than clocks as clocks is a bad idea.

 

[imbichie]

I wouldnt do this. Using things other than clocks as clocks is a bad idea.

But here all the changes are depends on the rising_edge(rx_ready).

 

[ya_montazar]

I wouldnt do this. Using things other than clocks as clocks is a bad idea.

that's true. but is there any suggestion to detect a non-clk signal edge??
somebody suggest this:

process(clk)
	begin
		if(rising_edge(clk))then
			tmp1 <= pulse;
			tmp2 <= tmp1;
		end if;
	end process;
	
	edge <= tmp1 and (not tmp2);

but the result is :

 

[TrickyDicky]

Thats the safest way to do it. (even better, clock the detection too.

 

[ya_montazar]

Thats the safest way to do it. (even better, clock the detection too.

but if we put a condition like "edge = '1'" the problem is that a signal rising edge occurs just one moment while "edge" width last (in this exp) 100ns. another problem is the "20ns" deferment; "pulse" edge occurs (for exp) in time "t" while edge start in time "t+20ns".
???

 

[TrickyDicky]

then delay your source signal so that the edge detection is co-incident with the delayed input.
This is pipelining, and is what happens all the time.

I notice your pulse is not synchronous with the clock. It must be synchronised with the clock to avoid any glitching and meta-stability. You synchronise it by passing it through 2 registers.

 

[ya_montazar]

got it!
the above code can detect the non-clk signal edge just when the clk is greatly faster than that signal. however it is not completely accurate.
the faster input clock, the much more precise signal edge detecting.