man optimize_registers
-clock clock_name
Specifies the name of the clock whose sequential cells are to be retimed.
-only_attributed_designs
Specifies that instead of the top-level design, only instances of those designs in the hierarchy below the current designs that
have the optimize_registers attribute set are retimed.
man set_optimize_registers
Sets the optimize_registers attribute on the specified designs
or on the current design, so that compile automatically invokes
the DC Ultra optimize_registers command to retime the design
during optimization.
It is easy to use built-in command "man" inside DesignCompiler session.
Thank you oratie ! Great answer! Now it's clear!
BTW, would re-timing on a clock path invoke future problems with LEC (Logic Equivalent Checking) or the tool only checks equivalency on the end-points?
Should re-timing invoke any future problems in the ASIC flow?
Thank you!
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oratie,
Could you also help with the commands, which should be used for logic cloning on the violated paths?
Thank you!
It's possible. Synopsys recommend to use side-file SVF (generated by DesignCompiler) for formal verification in Synopsys Formality. I do not know exactly about third-party tools.
Regarding logic cloning - I know only about register cloning:
set_register_replication
Sets the register_replication attribute on the specified sequen-
tial cells, thus allowing register replication on the objects.
Sets the register_replication attribute on object_list. This attribute
is used to specify how many copies the sequential cells are replicated.
When the option -num_copies is present, the register_replication
attribute value is the value of the option -num_copies. Otherwise, it
is the value of the option -max_fanout.