According to rules of this forum (
https://www.edaboard.com/help/terms/):
Use CODE/SYNTAX tags
How to proceed:
https://www.edaboard.com/threads/how-to-apply-code-and-syntax-tags.321025/
Regarding your question:
-> Google -> "assign verilog" -> first link
Should be
assign
select[1:0] = ...
In addition: port mapping while instantiation of the module can be done in two different ways i.e. “Port mapping by order” and “Port mapping by name“.
You're using port mapping by order, which is more error prone.
I suggest to use port mapping by name. Always.