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Syntax error in verilog

Mustaine

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In the example that i took from digital design by morris mano, there is a syntax error that i con not fix can you help me about that.
thanks in advance.
error code is = syntax error near "[". (line11)
note: undeclared symbol select, assumed default net type wire (line 14)
 

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niciki

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According to rules of this forum (https://www.edaboard.com/help/terms/): Use CODE/SYNTAX tags
How to proceed: https://www.edaboard.com/threads/how-to-apply-code-and-syntax-tags.321025/

Regarding your question:
-> Google -> "assign verilog" -> first link
Should be
assign select[1:0] = ...

In addition: port mapping while instantiation of the module can be done in two different ways i.e. “Port mapping by order” and “Port mapping by name“.
You're using port mapping by order, which is more error prone.
I suggest to use port mapping by name. Always.
 
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Mustaine

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According to rules of this forum (https://www.edaboard.com/help/terms/): Use CODE/SYNTAX tags
How to proceed: https://www.edaboard.com/threads/how-to-apply-code-and-syntax-tags.321025/

Regarding your question:
-> Google -> "assign verilog" -> first link
Should be
assign select[1:0] = ...

In addition: port mapping while instantiation of the module can be done in two different ways i.e. “Port mapping by order” and “Port mapping by name“.
You're using port mapping by order, which is more error prone.
I suggest to use port mapping by name. Always.
I didn't know the rules so thanks for the warning.
After i changed the the code the way you said, again it gives me error as below
what do i do wrong
 

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You never declared select in your code, so it defaults to a 1-bit wire type.

Add wire [1:0] select; after your module declaration and before the assign.
 

Mustaine

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You never declared select in your code, so it defaults to a 1-bit wire type.

Add wire [1:0] select; after your module declaration and before the assign.
thanks for your reply but after i added the code it still gives me the same error.
 

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You repeated your original mistake of putting the [1:0] in front of the name. See post #2.

Read a Verilog tutorial to learn the syntax, so far all your errors are basic syntax rule violations.
 

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