Hi, you define scan clock to be clk_i. Does clk_i drive the clock pins of your flops directly? Or is there some gating function that enables clk?
Hi,
I this RTL verilog is very simple as below,
module count(
counter,
rst_n,
clk
);
input clk;
input rst_n;
output [7:0] counter;
reg [7:0] counter;
always @(posedge clk or negedge rst_n)
if (!rst_n)
counter <= 0;
else
counter <= counter + 1;
endmodule
----------------------------------------------
DFT script,
read_file -f verilog ./src/count.v
current_design count
link
check_design
create_clock -period 80 -waveform [list 0 40] -name clk clk
set_input_delay 2.0 -clock clk [all_inputs]
set test_default_scan_style multiplexed_flip_flop
create_port -dir in scan_mode
create_port -dir in scan_en
create_port -dir in scan_clk
create_port -dir in scan_in
create_port -dir in scan_rst
create_port -dir out scan_out
compile -scan
set_dft_signal -view spec -type TestMode -port scan_mode -active_state 1
set_dft_signal -view spec -type Reset -port scan_rst -active_state 0
set_dft_signal -view spec -type ScanClock -port scan_clk
set_dft_signal -view spec -type ScanEnable -port scan_en -active_state 1
set_dft_signal -view spec -type ScanDataIn -port scan_in
set_dft_signal -view spec -type ScanDataOut -port scan_out
create_test_protocol
dft_drc -verbose
write -format verilog -hierarchy -output count_scan.v
set_dft_configuration -scan enable
set_dft_configuration -fix_set enable
set_dft_configuration -fix_clock enable
set_dft_configuration -fix_bus enable
set_dft_configuration -fix_bidirectional enable
set_dft_configuration -control_points enable
insert_dft
--------------------------------------------------------
DRC Warings,
-----------------------------------------------------------------
Begin Pre-DFT violations...
Warning: Clock input CK of DFF counter_reg[7] was not controlled. (D1-1)
Warning: Clock input CK of DFF counter_reg[2] was not controlled. (D1-2)
Warning: Clock input CK of DFF counter_reg[3] was not controlled. (D1-3)
Warning: Clock input CK of DFF counter_reg[4] was not controlled. (D1-4)
Warning: Clock input CK of DFF counter_reg[5] was not controlled. (D1-5)
Warning: Clock input CK of DFF counter_reg[6] was not controlled. (D1-6)
Warning: Clock input CK of DFF counter_reg[1] was not controlled. (D1-7)
Warning: Clock input CK of DFF counter_reg[0] was not controlled. (D1-8)
Warning: Reset input RN of DFF counter_reg[7] was not controlled. (D3-1)
Warning: Reset input RN of DFF counter_reg[2] was not controlled. (D3-2)
Warning: Reset input RN of DFF counter_reg[3] was not controlled. (D3-3)
Warning: Reset input RN of DFF counter_reg[4] was not controlled. (D3-4)
Warning: Reset input RN of DFF counter_reg[5] was not controlled. (D3-5)
Warning: Reset input RN of DFF counter_reg[6] was not controlled. (D3-6)
Warning: Reset input RN of DFF counter_reg[1] was not controlled. (D3-7)
Warning: Reset input RN of DFF counter_reg[0] was not controlled. (D3-8)
--------------------------------------------------------------------------
insert_dft message,
Information: Starting test design rule checking. (TEST-222)
Warning: Violations occurred during test design rule checking. (TEST-124)
Information: Test design rule checking completed. (TEST-123)
Running Autofix
Architecting Test Points
Information: Starting test design rule checking. (TEST-222)
Warning: Violations occurred during test design rule checking. (TEST-124)
Information: Test design rule checking completed. (TEST-123)
* "/data/soc1/testc/test/bd3202/rtl/syn/mask/count_CONTROL_FORCE.v" file correctly generated *
Loading verilog file '/data/soc1/testc/test/bd3202/rtl/syn/mask/count_CONTROL_FORCE.v'
Detecting input file type automatically (-rtl or -netlist).
Running DC verilog reader
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Compiling source file /data/soc1/testc/test/bd3202/rtl/syn/mask/count_CONTROL_FORCE.v
Presto compilation completed successfully.
Removing netlist file '/data/soc1/testc/test/bd3202/rtl/syn/mask/count_CONTROL_FORCE.v'...
Structuring 'count_CONTROL_FORCE'
Mapping 'count_CONTROL_FORCE'
Warning: Clock information for all sequential cells of design is missing. (TEST-374)
Architecting Scan Chains
Mapping New Logic
Information: Scan insertion did not build any scan chains. (TEST-176)
Information: Scan routing is not complete. Signals 'serial or scan_enables' need to be routed. (TEST-899)
Information: DFT insertion was not successful. There were unrecoverable processing errors. (TEST-211)
In scan mode , clock is not controllering the registers, you can give the clk as a scanclock signal , below is one of the way:
read_file -f verilog rtl.v
current_design count
check_design
link
create_clock -period 80 -name clk -waveform {0 40} clk
set_input_delay 2.0 -clock clk [all_inputs]
create_port -dir in scan_en
create_port -dir in scan_in
create_port -dir out scan_out
set_dft_signal -view existing_dft -type Reset -port rst_n -active_state 0
set_dft_signal -view existing_dft -type ScanClock -port clk -timing {45 55}
set_dft_signal -view spec -type ScanEnable -port scan_en -active_state 1
set_dft_signal -view spec -type ScanDataIn -port scan_in
set_dft_signal -view spec -type ScanDataOut -port scan_out
compile -scan
create_test_protocol
dft_drc -v
insert_dft
Hope , it will work.
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