library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Poller is
port(Clock, nreset : in std_logic;
Req : in std_logic_vector(3 downto 1) :="000";
Ack : out std_logic_vector(1 downto 0));
end Poller ;
architecture Behavior of Poller is
type states is (None, Req1, Req2, Req3);
signal state : states;
begin
moore : process (Clock, nreset)
begin
if nreset = '1' then
state <= None;
elsif (Clock'event and Clock='1') then
case state is
when None =>
if req(3) ='1' then
state <= Req3;
elsif req(2) ='1' then
state <= Req2;
elsif req(1) ='1' then
state <= Req1;
end if;
when Req1 =>
if req(3) ='1' then
state <= Req3;
elsif req(2) ='1' then
state <= Req2;
elsif req(1) ='1' then
state <=Req1;
end if;
when Req2 =>
if req(3) ='1' and req(2) ='0' and req(1) ='0' then
state <= Req3;
elsif req(3) ='1' and req(2) = '1' and req(1) ='0' then
state <= Req3;
elsif req(3) ='1' and req(2) ='0' and req(1) ='1' then
state <= Req3;
elsif req(3) ='0' and req(2) ='1' and req(1) ='0' then
state <= Req2;
elsif req(3) = '0' and req(2)='0' and req(1) ='1' then
state <= Req1;
end if;
when Req3 =>
if req(3) = '1' and req(2) ='0' and req(1) ='0' then
state <= Req3;
elsif req(3) ='1' and req(2) ='1' and req(1) ='0' then
state <= Req2;
elsif req(3)='1' and req(2) ='0' and req(1) ='1' then
state <= Req1;
elsif req(3) ='0' and req(2) ='1' and req(1) ='1' then
state <= Req2;
elsif req(3) ='0' and req(2)='1' and req(1) ='0' then
state <= Req2;
elsif req(3) ='0' and req(2) ='0' and req(1) ='1' then
state <= Req1;
end if;
end case;
end if;
end process;
Ack <= "00" when (state=None) else
"01" when (state=Req1) else
"10" when (state=Req2) else
"11";
end Behavior;