Hi:
at synthesis step,u can do as follow:
My design is a synchronous reset system;
SYNTHESIS
I had done work about this step)
set_idel_network [get_ports [list reset_in1 reset_in2 xxx]
set_false_path [get_ports [list reset_in1 reset_in2 xxx]
set_dont_touch_network [get_ports [list reset_in1 reset_in2 xxx]
just setting to the reset port, it's enough!
Then you need to analysis the timing with the PrimeTime best ,maybe exist some paths that the cell delay is very very large, then you should analysis it, eg a AND gate (AND_reset_in1 & AND_data_net = AND_out (eg, delay incr 30.0) ), that the reset_in1 net passed a and logic, inducing this problem, of course maybe other operations inducing the problem, you should analysis the path, then need to set_ideal_network to the output the gate that casued the problem(eg,AND_out in this example,set_ideal_network [get_pins xxx/xxxx/AND_out]) ;
2 P&R step(this step i just have heared some ideas)
add buffer to the input port, and the added numbers should be appropriate, maybe after this opration some problems is solved.
Of course you can dispose the reset_in1/2 trees like treating the clock tree ,it's a good method.
But, to balance the reset tree can't solve the RECOVERY/REMOVAL problem. having very good idea?
How to solve the timine vilovation caused by them is important too. And the front-end engineer should add the reset manage logic (eg,another DFF(whose input is '0' if '0' is reset enable) befor the reset_in1 ) to solve the problem;
And if the design have 2 clocks clk1 and clk2(asynchoronous) ,should have reset_in1 and reset_in2 to reset clock1 and clock2 part separatly?if using the same reset_in signal ,maybe inducing the reset operation asynchoronous problem during diffrent clocks , have a better way to deal with it?