Synchronous receive Verilog program help

[Felixx68]

Hello Guys,

New to EDA Board. I'm a student trying to write a program to receive bytes from a micro controller on an FPGA. There are 3 pins for the communication, data pin, enable pin, clock pin. I have written the following code and it receives, but the data it is showing to be received is wrong. Wondering if you guys can look at it and tell me what you think.

Thank you!
JMac

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module temp_rx(
        input clk,
        output [9:0]temp_raw,
        input data_rc,
        input enable_rc,
        input cnt_clk  );
 
reg [15:0] temp_data;
reg [9:0] temp_raw;
reg busy;
reg count = 1'b0;
reg cnt_change;
 
always @( posedge clk ) begin
         cnt_change = count^cnt_clk;
 
         if((enable_rc == 1'b1)) begin
                  busy =  1'b1;
 
                  if((cnt_change == 1'b1)) begin
                         temp_data = temp_data << 1
                         temp_data[0] = data_rc;
                  end else begin
                         temp_data = temp_data;
                  end
 
         end else begin
                  busy = 1b'0;
         end
 
         count = cnt_clk;
end
 
always @( posedge clk ) begin
         if ((busy == 1'b0)) begin
                  temp_raw <= temp_data;
         end
end
 
endmodule

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[ads-ee]

Obvious problems:

1) You've only written SW prior to writing Verilog, Verilog isn't SW it represents HW.

2) Don't use blocking '=' in a clocked always block (I know you used it because the shift wasn't working correctly).

3) It looks like you are using an higher speed clock to sample the lower speed signals data_rc, enable_rc, and cnt_clk. If so have you heard of metastability? If not you should read about it. In simulation things might look like they work, but in real life you may end up with intermittent failures.

4)
temp_data = temp_data << 1
you're missing the ; at the end
temp_data[0] = data_rc;
this follows the previous line and this won't synthesize correctly, due to the blocking assignment.
To create a shift register you should be writing the following code:
temp_data <= {temp_data[14:0], data_rc};

Other than that you need to run a simulation with a testbench to stimulated the design inputs. As you didn't supply the testbench and the code has syntax errors, I didn't attempt running it.

regards

 

[Felixx68]

Ads-ee,

Sorry for the syntax errors, I was not able to copy my code directly and was entering it onto the forum from my phone. Thank you for your help. As far as meta stability goes, it is my understanding that I can just run the signals through a couple of registers (flip-flops) and that will make it a lot better. Am I correct in this assumption? Do I just need to run the cnt_clk through, or should I run all three signals through, due to signal timing?

Thank you,
Jmac

 

[ads-ee]

Yeah, using a phone interface doesn't work too well.

Unless the signals from the micro are synchronous to that higher speed clock then yes synchronize all three of them. Your "high speed" clock better be at least 3x faster (better yet faster) than the cnt_clk frequency or you'll have issues with re-synchronizing the signals.