Apr 3, 2005 #1 R rrk Junior Member level 1 Joined Mar 1, 2005 Messages 15 Helped 2 Reputation 4 Reaction score 2 Trophy points 1,283 Activity points 1,378 I have to design a synchronous 3*3 bit multiplier in VHDL without using the operator *.It has to be a FSM . I tried several times but the outputs are not correct. Can someone help me with any resources online or maybe a some guideline steps plz!
I have to design a synchronous 3*3 bit multiplier in VHDL without using the operator *.It has to be a FSM . I tried several times but the outputs are not correct. Can someone help me with any resources online or maybe a some guideline steps plz!
Apr 4, 2005 #2 bibo1978 Full Member level 4 Joined May 1, 2004 Messages 210 Helped 12 Reputation 24 Reaction score 6 Trophy points 1,298 Activity points 2,548 why do u use an FSM ? what kind of multiplier do u want to do signed or unsigned? what kind of FPGA you r using?
why do u use an FSM ? what kind of multiplier do u want to do signed or unsigned? what kind of FPGA you r using?
Apr 4, 2005 #3 R Renjith Full Member level 3 Joined Jan 3, 2005 Messages 173 Helped 15 Reputation 30 Reaction score 6 Trophy points 1,298 Location India Activity points 1,710 Hi rrk, if u r not supposed to use a * operator, then use loops in ur coding to perform repetitive addition.
Hi rrk, if u r not supposed to use a * operator, then use loops in ur coding to perform repetitive addition.
Apr 4, 2005 #4 A au_sun Full Member level 2 Joined Aug 5, 2004 Messages 147 Helped 15 Reputation 30 Reaction score 4 Trophy points 1,298 Activity points 1,184 hi rrk, why cant u try any multiplier algorthim such as booth, bough-wooley ,