Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Synchronous FET controller disabler circuit

Status
Not open for further replies.

cupoftea

Advanced Member level 5
Joined
Jun 13, 2021
Messages
2,802
Helped
55
Reputation
110
Reaction score
120
Trophy points
63
Activity points
14,785
Hi,
The attached circuit is for use with synchronous FET controllers for Bridge's/Forwards.

So, the attached is a circuit which disables a synchronous FET controller whenever the power supply loading goes below 30%.
This is needed to avoid reversing current in the output inductor, which then causes overvoltages when the synch FET goes OFF.
The circuit also re-enables the controller when loading goes >30%...but does this after a delay of some 1 second or so.
Please can you see any opportunities for reducing component count?

****EDIT.....my sincere apologies...i forgot i put this in the Analog section (as below) END OF EDIT*****


[please could the above thread be deleted from the Analog section if at all possible?....Apologies for this....i stupidly forgot i put it there.]
 

Attachments

  • Delayed enable1.jpg
    Delayed enable1.jpg
    178.5 KB · Views: 99
  • Delayed enable1.zip
    2.1 KB · Views: 94

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top