Synchronous Counter Using D- Flip Flop(Verilog)

[lmr_fatih]

Hello everyone. I am new in Verilog. I want to make a prime number counter 1 to 63 with states. And i will use D-Flip Flop. I don't know how to write state's code on Verilog. Can anyone write the code of the picture?



Thank You!

 

[mrflibble]

Can you explain how prime numbers are related to the shown picture for which only people that have homework due this monday are going to write any code?

 

[lmr_fatih]

this picture is only an example. There must be states: 2 --> 3 --> 5 --> 7 --> ... 59--> 61 -->2 I want to make this thing with gates. I have found truth table then i did k-map and i found the input functions of D-Flip Flop(D1, D2, D3, D4, D5, D6) . Everything is OK but i don't know how to write on verilog

 

[FvM]

Building logic with FFs and gates is structural design. it can be described in Verilog, but doesn't use states. Or you write a behavioral description, define states and the transition conditions. The Verilog compiler translates the design to FFs and gates.

 

[ads-ee]

Can anyone write the code of the picture?
View attachment 108618

You're lucky I wasn't the first one to reply to this post...I would have given you the following code:

---

Code Verilog - [expand]
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module a4bit_sync_dwn_cntr (
  input c,
  output reg [3:0] q
);
  always @ (posedge c) begin
    q <= q + 1;
  end
endmodule

---

which is your 4-bit synchronous counter using D-Flip-flops. If your example doesn't show what you are trying to accomplish, then you probably shouldn't add it.

What you want is more like this:

---

Code Verilog - [expand]
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module prime_cntr (
  input c, r,
  output reg [5:0] primes
);
  always @ (posedge c) begin
    if (r) begin
      primes <= 2;
    end else begin
      case (primes)
        2 : primes <= 3;
        3 : primes <= 5;
        5 : primes <= // you add the reset
        // ...
        63 : primes <= 2;
        default : primes <= {6{1'bx}}; // if a transition is wrong the output will go X.
      endcase;
    end
  end
 
endmodule

---

 

[mrflibble]

You're lucky I wasn't the first one to reply to this post...I would have given you the following code:

Well, he got me at prime numbers. And then lost me again when showing a picture that has nothing to do at all with prime numbers. Just a regular boring down counter with no relation whatsoever to prime numbers.

Sound like the OP just wants a 6-bit ROM with 18 entries dressed up as a state machine. (*) Or maybe his assignment says "states", but that is really just a challenge by his prof to come up with an implementation that isn't as stupid as the assignment calls for.

PS: as for the code ... _down_ counter. At least that part is correct in the picture label.

(*) yes yes, memory is a state machine and a state machine is memory.