synchronous clocks and data signal passing.

[sun_ray]

A signal named sig1 is generated with width 4T in one clock domain Clk1 whose time period is T. This signal needs to be transferred to another clock domain Clk2 where the clock of Clk2 is derived from the clock of Clk1 by a divide by 2 circuit. So the time period of clock of Clk2 is 2T. How can this signal sig1 be passed from Clk1 to Clk2 safely?

Another signal named sig2 is generated with width T in Clk1. How can we transfer it safely to Clk2 domain?

 

[mail4idle2]

do a cycle extension of the sig1 in clk1 domain such that clk2 domain will sample it with out fail

 

[sun_ray]

do a cycle extension of the sig1 in clk1 domain such that clk2 domain will sample it with out fail

Please note that sig1 has time period of 4T. The clk1 and clk2 have time period of T and 2T respectively. How can a signal extension of sig 1 is required in this case? What circuit shall you use for signal extension? Is there necessity of any synchronizer in this situation?

Regards

 

[ads-ee]

It's been a while since I've used ASIC tools, but you should not cut timing between the clk1 and clk2 clock domains as you have a valid path between the two. As both clocks are derived from the same base clock of T period, they are inherently synchronous, but may have skew, which should be accounted for in the place and route and timing analysis.

 

[sun_ray]

It's been a while since I've used ASIC tools, but you should not cut timing between the clk1 and clk2 clock domains as you have a valid path between the two.

What do you mean by you should have cut timing. We agree that the clocks are synchronous. But you need to detect them.

Regards

 

[ads-ee]

I said you should not cut the timing (arc) between clock domains.

Why would you detect the clocks, you were asking about transferring signals from clk1 to clk2 domains and how to time them. I told you don't do anything but make sure the two clock domains are used in timing analysis as they are synchronous to each other. Just make sure you analyze the static timing reports for any setup or hold violations between the two domains as they are valid paths.

 

[sun_ray]

I said you should not cut the timing (arc) between clock domains.

Why would you detect the clocks, you were asking about transferring signals from clk1 to clk2 domains and how to time them. I told you don't do anything but make sure the two clock domains are used in timing analysis as they are synchronous to each other. Just make sure you analyze the static timing reports for any setup or hold violations between the two domains as they are valid paths.

I understand what you are stating. But what circuit shall be required is not still replied. The thread was started to ask the circuit.

Regards

 

[sharath666]

Transfer of control signals can be done by a 2 flop synchronizer. Transfer of data signals can be done by synchronizing the control and using the synchronized output to latch the data.

 

[imbichie]

By considering clk1 and clk2 are synchronous clocks:
sig1 is 4T long, so you can directly sample the sig1 in clk2 domain, there wont be any sync issue.
For sig2 which have duration only T: if the signal updation is always happening only after 2T period, then you can use a pulse stretching circuit (just flop the sig2 and OR the sig2 and the sig2_flop output) to extend the sig2 T duration pulse to sig2_2T pulse,and you can sample the sig2_2T signal in the clk2 domain. But make sure the the updation of sig2 will be halt at least 2T period.