rajesh0therascal
Newbie level 3
Hi,
I have 16 KHz clock on board. I have to derive 1 Hz clock for internal logic application. Kindly suggest me a methodology for that. Derived clock should be synchronous with master clock. I've written a VHDL code, but it is out of sync and it has glitches in post synthesis simulation. Kindly help..
Regards,
Rajesh.
I have 16 KHz clock on board. I have to derive 1 Hz clock for internal logic application. Kindly suggest me a methodology for that. Derived clock should be synchronous with master clock. I've written a VHDL code, but it is out of sync and it has glitches in post synthesis simulation. Kindly help..
Regards,
Rajesh.