I guess everything was said by sunjimmy and flatulent, but the things are always better to explain in more views, so that the practical consequences became completely clear:
Asynchronous reset (often also caller "clear") does reset /clear the state imediately, independently of the clock edges. It usually overrides any clock-synchronized actions, so it keeps the system/component firmyin "reset-state" while active.
Synchronous reset is always related to the clock active edge. It is for a register equivalent of loading with "reset-value" - usually zeros. It has no effect outside the active clock edge (just be aware setup and hold times around the edge -see below).
The sister functions: synchronous preset / asynchronous preset behave similarly, except they set a register's value (usually) to "1" instead of "0". Thus the asynchronous one is more powerul than the synchronous one and always immediate in it's action.
As flatulent points out, having pulses too narrow and not respecting setup time/hold time for the synchronous signal, may lead to something called metastability, and the consequences can be quite unexpected, and completely unpredictable. Therefore, if the synchronous reset/preset is not stable at/near the clock edge (i.e. stable before "setup time" or until "hold time"), or the pulse is shorter than the data sheet minimum, be aware! The result will not be predictable nor reliable.