synchronized serial data capture to registers

[sharak]

hi all!
I am new to this site. I want to know how to capture a serially coming data to registers bit-wise.
example : data_in is the serial input data synchronized with clock.
reg A should contain the first bit of serial input data
reg B should contain the first bit of serial input data
reg C should contain the first bit of serial input data

How do i program this?

please help me out.

thanks in advance

- - - Updated - - -

*sry
A with first bit
B with second bit
C with third bit

and i need program in verilog language

 

[dipin]

hi,
what is your input data width?

you said it serially right?
is it means 1 bit per clock cycle or n bit( say 3 bit) per clock cycle
if it 1 bit per clock cycle , how is your data format, i mean how you distinguish one data from next ?

regards

 

[sharak]

sir,
it is 1 bit per clock cycle ans simulstion s 100us long and each bit s 100ns long

 

[dpaul]

it is 1 bit per clock cycle ans simulstion s 100us long and each bit s 100ns long

I think you need to explain more clearly.

*sry
A with first bit
B with second bit
C with third bit

You data is coming in serially, so what happens to the 4th bit? Does it go again to regA or another regD?

What is the rate of your serial data?

 

[ads-ee]

If you can't do shifting (assumption) of the A B C registers then you need to perform a demultiplex. How things are aligned and how you determine the alignment is important. This Verilog snippet shows you one way to demultiplex the data_in into A, B, and C registers.

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Code Verilog - [expand]
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always @ (posedge clk) begin
  // rollover 0-2 counter
  if (bit_cnt < 2) begin
    bit_cnt <= bit_cnt + 1;
  end else begin
    bit_cnt <= 0;
  end
 
  // demultiplexes the data_in into the three regsiters
  case (bit_cnt)
    0 : A <= data_in;
    1 : B <= data_in;
    2 : C <= data_in;
    default : unspecified <= 'bx;
  endcase
end

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FYI, Verilog is a hardware description language, it does not make a very good programming language akin to something like C++. So when you need to write something in Verilog it is almost always best to think of the circuit you need to design, before writing a single line of a Verilog description.

 

[KlausST]

Hi,

Usually one uses a shift register to create parallel data from serial incoming data stream.
Do you have a serial clock signal?
How many bits are in one frame?
Wow do you recognize frame sync?
Do you want to output each bit individually after it is received, or do you want to update the whole frame?

A 100ns pulse within a 100us bit rate is only 1/1000. Is this really useful?
What system clock is available in your FPGA?
Is it synchronized to serial clock?

Draw a timing diagram.

Klaus